Francesca Sica
Design of an edge-oriented vector accelerator based on RISC-V "V" extension.
Rel. Guido Masera, Maurizio Martina, Michele Caon, Walid Walid. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022
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Abstract
In the last decade, the ever-increasing diffusion of machine learning algorithms for digital signal processing has drastically changed the hardware processing requirements for edge devices. These systems have to manage a large amount of data while often still responding to some events in real-time. To elaborate the information acquired by these systems, a suitable paradigm can be edge computing: instead of directly sending raw data to remote central servers, this can be partially processed close to where it is collected so that a smaller amount of elaborated data is sent to central systems, reducing the response time, the network-overloading and the overall power budget required.
To manage such a high quantity of data, it is important to choose efficient architectures exploiting parallel computing: vector processors have demonstrated to be a promising solution
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