Simone Romeo
ARISE: Integration of an Approximate and Reconfigurable Spatial Array on a RISC-V-Based Platform.
Rel. Maurizio Martina, Guido Masera, Michele Caon, Emanuele Valpreda, Flavia Guella. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
Abstract
Leveraging recent advancements in computational power, data availability, and algorithmic techniques, Convolutional Neural Networks (CNNs) have become widely adopted for processing images and audio due to their efficient handling of grid-like data. However, CNNs, and Deep Neural Networks (DNNs) in general, demand extensive computational resources and memory usage, impacting both power efficiency and hardware cost. The growing usage of CNNs on edge devices has driven the development of specialized hardware accelerators, like systolic arrays, to reduce data transfer overhead and enhance performance by efficiently handling the high parallelism and data throughput demands. To meet the resource and power constraints of IoT and edge devices, hardware-software optimization techniques like quantization and approximate computing are further employed.
Quantization reduces DNN precision to decrease memory footprint and hardware requirements, while approximation further minimizes computation costs in terms of area and power, trading some accuracy for efficiency
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