Lorenzo Capobianco
Open Hardware, Hidden Risks: Mitigating passive power side-channel leakage in RISC-V microcontrollers.
Rel. Guido Masera, Mattia Mirigaldi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
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Abstract
Today's digital infrastructure is based on secure telecommunications which is crucial in all kinds of applications, from electronic payments and transaction to smart homes. In such a context, data security and confidentiality are fundamental requirements. Encryption algorithms ensure these objectives by transforming sensitive data into unintelligible information, decipherable only with the correct secret key. While these algorithms are mathematically secure, their hardware implementations remain vulnerable to side-channel attacks (SCAs), which exploit physical leakages such as timing or power consumption rather than algorithmic weaknesses. Correlations between power traces and the internal state of a device can reveal secret information, undermining cryptographic protections.
This thesis investigates the vulnerability of standard encryption schemes to SCAs, with a focus on resource-constrained embedded systems based on the royalty-free RISC-V architecture
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