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List of theses with "Roascio, Gianluca as relator"

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Number of items: 3.

13 April 2022

[img] Simone Peraccini. Design of a RISC-V Based Microarchitecture for Secure Embedded Systems. Rel. Paolo Ernesto Prinetto, Gianluca Roascio. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

28 October 2022

[img] Luca Dalmasso. MC2101: A RISC-V-based Microcontroller for Security Assessment and Training. Rel. Paolo Ernesto Prinetto, Gianluca Roascio. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

[img] Alessandro Iandoli. PROLEPSIS: Binary Instrumentation Tool for Control-Flow Integrity in ARM and RISC-V. Rel. Paolo Ernesto Prinetto, Gianluca Roascio. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

This list was generated on Sun Dec 4 22:51:37 2022 CET.