polito.it

Login

Webthesis
Libraries

Thesis by Neri, Marcello

Group by: Item Type | No Grouping

Jump to: Thesis

Number of items: 1.

Thesis

Marcello Neri. Design of a fault tolerant instruction decode stage in RISC-V core against soft and hard errors. Rel. Stefano Di Carlo, Alessandro Savino, Maurizio Martina, Guido Masera, Luca Maria Cassano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

This list was generated on Sat Dec 9 22:42:41 2023 CET.

Contacts