High-Level Synthesis Exploration of Cache size Effects in FPGA-Based subgraph Isomorphism Acceleration
Seyedehzahra Mirabedini
High-Level Synthesis Exploration of Cache size Effects in FPGA-Based subgraph Isomorphism Acceleration.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
