This thesis optimises test architecture for RISC-V System-on-Chip designs by improving observation coverage for Software-Based Self-Test on the open-source CVA6 processor. As silicon now drives appliances, vehicles, smartphones, and medical devices, robust SoCs and thorough testing are essential. Designs that are easier to test raise yield and shorten time-to-market; periodic online tests executed during normal operation improve reliability and enable at-speed checks. Developed with STMicroelectronics, the work extends an earlier CVA6 study that boosted SBST by inserting observation monitors at random RTL points. Here, randomness is replaced with a principled selection of internal signals whose fault effects are masked and cannot reach primary outputs.