Giacomo Sansone
From Gated-SSA to Out-of-Order Dataflow Circuits.
Rel. Mariagrazia Graziano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2025
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Abstract
In the past 10 years, both companies and universities started pushing to have working and reliable High Level Synthesis tools. This is a mandatory step for the spread and success of FPGAs across many industries: people without a hardware background are supposed to be able to rely on these tools, thus adopting a framework which allows them to deploy hardware starting from what they are more comfortable with, software. Two main paradigms arose: static-HLS instantiates a datapath to perform computation and a controller to steer the data and the execution flow. While this approach is intuitive and pragmatic, it lacks flexibility, since the scheduling of operations is decided at compile-time.
This results from the purely static nature of the approach
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