High-Level Synthesis (HLS) enables rapid prototyping of application-specific hardware, allowing designers to develop hardware using C/C++ instead of hardware description languages (HDL). HLS directives (pragmas) provide optimization mechanisms for balancing performance and resource utilization. However, as the number of applied optimizations increases, the number of possible design configurations grows exponentially. Evaluating each design with HLS tools incurs significant computational and time costs, leading to slow and inefficient design space exploration. To accelerate this process, machine learning models, particularly graph neural networks (GNN), have been used to predict the quality of results (QoR) from pre-synthesis representations. However, existing methods still require improvements due to issues such as significant prediction errors caused by information loss during graph convolution and pooling.