This thesis addresses the implementation of a high-performance Low-Density Parity-Check (LDPC) code decoder, crucial for achieving Ultra Reliable Low Latency Communication (URLLC) as envisioned by the 3GPP consortium. Future technologies like the tactile internet, autonomous vehicles, and telemedicine require robust Forward Error Correction (FEC) methods, and LDPC codes are ideal due to their rapid convergence and reliability in noisy environments. However, high-throughput LDPC decoders often face challenges related to area efficiency and routing congestion. To overcome these limitations, this work introduces a fully reconfigurable, fully unrolled, and parallel LDPC decoder using the Reconstruction-Computation-Quantization (RCQ) paradigm. The architecture supports Offset-Min-Sum (OMS) and Min-Sum (MS) decoding algorithms, optimizing the use of fine-grain pipelining to achieve higher throughput.