Nowadays, the rise of the RISC-V instruction set architecture (ISA) has led to an increasing interest towards the development of royalty-free and open-source products. Thanks to RISC-V, hardware architectures can be customised to suit specific product needs, offering a flexible and scalable approach that benefits both Original Equipment Manufacturer (OEM) producers and final consumers. To design products, companies strongly rely on simulations to explore the various design choices and the possible flaws of a design, reducing both the development times and costs. Being a rather recent technology, however, there is still a lack of comprehensive simulation frameworks for RISC-V cores, especially for ones targeting both functional and extra-functional aspects such as power consumption.