Bruno Coppolelli
Modeling of Tunnel-FETs: accurate calibration of numerical and semi-analytical models.
Rel. Simona Donati Guerrieri, Alberto Tibaldi. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2022
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Abstract
Making transistors smaller is a process called transistor scaling and it has been the most important factor in increasing a computer’s computational power, speed, and memory. Indeed, the smaller transistors are, the more they can be integrated into a chip, which will feature more complex functions. This has been clear since the beginning of electronics, the reason why great efforts have been made on miniaturization. This idea led Gordon Moore to predict in 1975 that the number of transistors in a dense integrated circuit (IC) would double every two years. This prediction, driven by transistors size reduction, has come true ever since it was made, so it became the so-called Moore’s law.
However, the miniaturization process is now reaching its limits due to the increasing difficulties of silicon and voltage supply scaling
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