Design of a fault tolerant instruction decode stage in RISC-V core against soft and hard errors
Marcello Neri
Design of a fault tolerant instruction decode stage in RISC-V core against soft and hard errors.
Rel. Stefano Di Carlo, Alessandro Savino, Maurizio Martina, Guido Masera, Luca Maria Cassano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021
