Processors that support Out-of-Order (OoO) execution are widely used today, forming the foundation of modern processors. The ability to reorder the execution of instructions makes these processors, already widely adopted in consumer and High-Performance Computing fields, attractive for modern Low-Power Heterogeneous Systems, where it is essential to coordinate a large number of peripherals such as Coprocessors, Accelerators, GPUs, etc., with arbitrary latencies. Being able to execute instructions as soon as their operands are available, rather than in the order specified by the user, helps to mask the latencies of these peripherals while simultaneously increasing Instruction Level Parallelism (ILP), thus enhancing performance.