Convolutional Neural Networks (CNNs) are nowadays ubiquitous thanks to their remarkable performance in a wide spectrum of tasks, from computer vision to speech recognition. However, high task accuracy generally comes at the cost of increased power consumption, which is an incompatible feature with respect to the rising trend in moving computation towards the edge. In this context, PULP, an open-source microcontroller featuring an 8-core cluster based on RISC-V Instruction Set Architecture (ISA), is chosen as the target platform of this work. It provides a good trade-off between reconfigurability, required by the heterogeneity of applications and precluded to custom accelerators, and power optimization.