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ENIT
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Design of a fault tolerant instruction decode stage in RISC-V core against soft and hard errors

Marcello Neri

Design of a fault tolerant instruction decode stage in RISC-V core against soft and hard errors.

Rel. Stefano Di Carlo, Alessandro Savino, Maurizio Martina, Guido Masera, Luca Maria Cassano. Politecnico di Torino, Master of science program in Electronic Engineering, 2021