Design of a fault tolerant instruction decode stage in RISC-V core against soft and hard errors

Failures in electronic devices caused by radiation is one of the most challenging is-sues arising in the last decades. Nowadays, the radiation effects are crucial not only in the space environment, but also at the sea level, since transistor downscaling is affecting the characteristics of the integrated circuits. When operating in hostile environments, solid-state devices and integrated circuits may be directly struck by photons, electrons, protons, neutrons, heavy ions, or alpha particles causing alteration of their electrical properties. This puts at risk the reliability and integrity of thosedevices, leading also to possible catastrophic consequences if they occur in safety critical applications. The international standard IEC 61508 sets the requirements thata safety-related system must meet in order to be classified and certified according to its reliability level. For what concerns the hardware design, the mitigation against radiation effects ispossible by applying the concept of redundancy to all the components in the system. In this thesis project, the fault tolerant design of the Instruction Decode (ID) stage of the CV23E40P core, which is a RISC-V core, implementing the RV32IMC instruction set, is presented. The work developed in this thesis is included in a wider project that aims to make the entire CV32E40P core fault tolerant. The proposed design makes use of Error Correction Code (ECC) and N-Modular Redundancy (NMR) techniques which ensure fault tolerance against Single Event Effects (SEEs) to all thec omponent included in the stage. Specifically, the Hsiao code is one of the most suitable ECC from the hardware optimisation perspective. So, it is used in the design with Single Error Correction and Double Error Detection (SECDED) capabilities. As regards the NMR technique, for the purpose of the thesis, triplication (TMR) results the best trade-off between hardware overhead and fault tolerance level. In fact, the TMR uses the minimum level of redundancy to get capable to detect and correct single errors without suspending the program execution. However, in the state-of-the-art, some RISC-V cores already use these techniques to mitigate transient errors. The innovative side of this thesis work is the design of a specific partial solution against the permanent errors, besides the traditional techniques used against the transient ones. Specifically, the most critical component inthe ID stage from the radiation perspective is the register file, being the most extended component of the whole core. Its design provides for extra “supply” locations to replace the permanently damaged registers and allow the correct execution of the program in any of the most hostile situations. The effectiveness of the fault tolerant design of the ID stage is evaluated by means of the simulating approach. One transient fault is injected to each simulation of the core running the CoreMark benchmark program. The system implemented for the fault injection is based on TCL scripts which exploit special functions of QuestaSim simulator (i.e., the force command) for bit-flipping a single bit of the memory components in the stage. Under these conditions, the fault tolerant level reached against soft errors is between the 95% and the 100% with a confidence level of the 99%.