Antonia Ieva
Speed-up of RISC-V core using Logic-In-Memory operations.
Rel. Marco Vacca, Marco Ottavi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020
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Abstract: |
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Relators: | Marco Vacca, Marco Ottavi |
Academic year: | 2019/20 |
Publication type: | Electronic |
Number of Pages: | 113 |
Subjects: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering) |
Classe di laurea: | New organization > Master science > LM-29 - ELECTRONIC ENGINEERING |
Ente in cotutela: | KTH - Kungl. Tekniska Hogskolan (Royal Institute of Technology) (SVEZIA) |
Aziende collaboratrici: | UNSPECIFIED |
URI: | http://webthesis.biblio.polito.it/id/eprint/15369 |
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