Speed-up of RISC-V core using Logic-In-Memory operations - WebThesis

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Speed-up of RISC-V core using Logic-In-Memory operations

Antonia Ieva

Speed-up of RISC-V core using Logic-In-Memory operations.

Rel. Marco Vacca, Marco Ottavi. Politecnico di Torino, Master of science program in Electronic Engineering, 2020

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Relators

Marco Vacca, Marco Ottavi

Academic year

2019/20

Publication type

Electronic

Number of Pages

113

Course of studies

Master of science program in Electronic Engineering

Classe di laurea

New organization > Master science > LM-29 - ELECTRONIC ENGINEERING

Ente in cotutela

KTH - Kungl. Tekniska Hogskolan (Royal Institute of Technology) (SVEZIA)

URI

https://webthesis.biblio.polito.it/id/eprint/15369

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