25 Ottobre 2019

Hubert Couston. Verification, Identification and Elimination of parasitic structures in an integrated circuit to avoid unwanted triggering that could induce premature failure = Verification, Identification and Elimination of parasitic structures in an integrated circuit to avoid unwanted triggering that could induce premature failures. Rel. Carlo Ricciardi, Johan Bourgeat, Quentin Rafhay. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2019