List of theses with "Ottavi, Marco as relator" - WebThesis

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Antonia Ieva. Speed-up of RISC-V core using Logic-In-Memory operations. Rel. Marco Vacca, Marco Ottavi. Politecnico di Torino, Master of science program in Electronic Engineering, 2020

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This list was generated on Mon Feb 9 20:51:24 2026 CET.