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List of theses with "Macii, Alberto as relator"

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Jump to: 20 April 2018 | 16 April 2021
Number of items: 2.

20 April 2018

Giulio Milici. Fault tolerant L1 cache for the CORSAIR Multi-Core architecture. Rel. Alberto Macii. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2018

16 April 2021

[img] Sergio Mazzola. ISA extensions in the Snitch Processor for Signal Processing. Rel. Alberto Macii, Luca Benini, Samuel Riedel, Matheus De Araujo Cavalcante. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2021

This list was generated on Fri Dec 13 20:04:26 2024 CET.