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Thesis by Pala, Stefano

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Thesis

[img] Stefano Pala. Progetto di un generatore di clock per circuiti in tecnologia pNML = Clock generator design for pNML technology circuits. Rel. Maurizio Zamboni, Fabrizio Riente, Mariagrazia Graziano, Marco Vacca. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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