Livello precedente |
Stefano Moncalvo. Definition of a verification flow for High-Level Synthesis IPs: Case study on functional coverage applied to High Level Synthesis blocks in a C++ and Universal Methodology environment. Rel. Maurizio Martina, Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023