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Thesis by Moncalvo, Stefano

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Stefano Moncalvo. Definition of a verification flow for High-Level Synthesis IPs: Case study on functional coverage applied to High Level Synthesis blocks in a C++ and Universal Methodology environment. Rel. Maurizio Martina, Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

This list was generated on Sun May 19 19:55:08 2024 CEST.

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