Politecnico di Torino (logo)

Thesis by Feraco, Biagio

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Group by: Item Type | No Grouping
Jump to: Thesis
Number of items: 1.


[img] Biagio Feraco. FPGA-Based Framework for Hardware Acceleration of the HEVC Encoder. Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

This list was generated on Sat Jul 20 19:44:56 2024 CEST.