HEVC (High Efficiency Video Coding), the most recent standard for video compression, led to an huge increase of the encoding efficiency with the respect to the previous standards but, on the other hand, several tasks became highly time demanding and power consuming. This thesis proposes a fast, dynamically reconfigurable and flexible hardware accelerator for the SATD (Sum of Absolute Transformed Differences), that is one of the cost functions adopted by HM HEVC reference software.The developed hardware block follows all the specification given by HEVC and can work with every Transform Unit size from 8x8 up to 64x64.The accelerator is fast thanks to a highly parallelized architecture.