Instruction dispatch policy optimization for superscalar processors. On high performance CPUs implementing many different execution units, one problematic is making fast and good decision for incoming instructions steering to issue queues and execution units. Different parameters like execution units organization, data dependencies between instructions, instruction queues resource availability (…) should influence new instructions dispatch choice. The main goal of this work is studying and implementing various dispatch policies on a given high-end CPU in order to improve performance and simplify issue queues logic, within given timing constraints.