Development of hardware accelerators on FPGA for convolutional neural networks
Giulia Altamura
Development of hardware accelerators on FPGA for convolutional neural networks.
Rel. Mario Roberto Casu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018
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Abstract
The aim of this thesis is to develop an architecture to accelerate the operation of convolution performed by neural networks. In particular it is to implement a matrix-matrix multiplication by executing the equation "C = A*B*alpha + C*beta".
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