Fault tolerant L1 cache for the CORSAIR Multi-Core architecture

Giulio Milici

Fault tolerant L1 cache for the CORSAIR Multi-Core architecture.

Rel. Alberto Macii. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2018

Abstract

The purpose of the work of this thesis has been to design a fault tolerance system and therefore to find a solution to the presence of soft errors (they are errors not caused by hardware defects and generally have a transitory duration) in the L1 cache of the CORSAIR multi-core architecture, currently under development in the LISAN laboratories of CEA-Leti of Grenoble.