Modern System-on-Chip (SoC) designs manufactured in advanced technology nodes face increasingly critical interactions between power integrity and timing performance. As supply voltages scale down and current densities rise, localized IR-drop hotspots become more frequent and severe, reducing the effective VDD delivered to standard cells. This can cause disproportionate delay degradation in Vmin-sensitive cells, whose performance strongly depends on small voltage fluctuations. Consequently, timing failures that appear to stem from intrinsically weak logic paths are often driven instead by local power-delivery weaknesses: cells located in IR-drop hotspots operate at a reduced voltage, increasing their delay and ultimately inducing setup timing violations. This thesis addresses this coupled problem by proposing a methodology that mitigates IRdrop at its root cause, focusing on aggressor cells — cell instances whose switching activity, current profile, and physical placement contribute most to local supply-voltage collapse.