Near Field Communication (NFC) systems increasingly require both high performance and flexibility, especially in applications where real-time signal decoding must operate reliably under different communication conditions. Traditional fixed-function DSP solutions can achieve high efficiency, but they are often difficult to adapt when algorithms need to be updated or extended. This thesis investigates an alternative approach based on a programmable RISC-V architecture supported by dedicated hardware acceleration, with the aim of combining flexibility with the computational performance required for NFC decoding. The work focuses on the integration of the RIVIERA platform, built around the CV32E40X RISC-V core, the CORE-V-XIF extension interface, and a dedicated coprocessor, into an existing NFC System-on-Chip environment.