As industrial ASIC designs increase in complexity, driven by the integration of multiple components and advanced clocking schemes, traditional gate-level Design-for-Testability (DFT) insertion often becomes a late-stage bottleneck. In conventional flows, DFT structures are inserted and validated only after synthesis; consequently, errors related to integration DFT and RTL are detected late in the project cycle, making debugging difficult, costly to fix and increasing the risk of significant schedule delays. This thesis details the successful deployment of a "shift-left" strategy on a 600k-gate ASIC designed for industrial applications in STMicroelectronics CMOS040 technology. This approach moves the insertion and validation of test structures directly into the Register Transfer Level (RTL) code, rather than waiting for the availability of a synthesized gate-level netlist.