In recent years, hardware architectures have evolved significantly, drawing increasing attention toward reconfigurable and parallelized models — systems capable of balancing flexibility and performance. The growing demand for such solutions has led Coarse-Grain Reconfigurable Architectures (CGRA) to become one of the most widely adopted approaches, as they can adapt to different computational problems and are particularly suitable for numerical and data-parallel applications. This thesis focuses on the design of a parametric CGRA composed of an NxN matrix of Processing Elements (PEs), where both the size and the interconnectivity between PEs can be modified. A Direct Memory Access (DMA) communication system has been integrated to generate AXI-Stream data flows, ensuring efficient frame loading and continuous data transfer toward the matrix.