This thesis addresses the hardware–software co-design scheduling problem for real-time systems involving a single CPU and multiple reconfigurable Field Programmable Gate Arrays (FPGAs). The problem requires assigning tasks with precedence, release, and deadline constraints to either the CPU or an FPGA, while respecting reconfiguration overheads and minimizing a composite cost that balances scheduling delay and hardware usage. Building on the seminal work of Ali et al.~\cite{ali2012}, who introduced a time-indexed mixed-integer programming (MIP) formulation, we first replicated and validated the original model to establish a performance baseline. While the MIP approach guarantees optimal solutions for small instances, its scalability is limited by the exponential growth of variables and constraints.