Verification has historically been a critical challenge in Application-Specific Integrated Circuit (ASIC) designs due to their fixed nature and high cost of post-silicon errors, today, the increasing complexity of Field Programmable Gate Arrays (FPGA) is driving a similar need for rigorous verification also for digital designs. As a result, traditional lab-based methodologies are proving insufficient for modern reconfigurable systems, especially in aerospace applications where they are becoming widely adopted due to their flexibility and reliability in the harsh conditions of space. This highlights the need for formal verification approaches, which can help reduce time-to-market, whereas over 60% of the design cycle is spent on verification, with nearly 40% dedicated to debugging.