he increasing demand for high-performance computation in fields such as signal processing, scientific computing, and embedded systems has highlighted the need for specialized hardware accelerators. Several architectural solutions exist, including Graphics Processing Units (GPU s), Field Programmable Gate Arrays ( FPGA s), Application Specific Integrated Circuits (ASICs), and Coarse Grained Reconfigurable Architectures (CGRAs). The objective of this thesis is the design of a generic CGRA architecture capable of operating on floating point data. The processing elements within the array support a broad range of functions, including arithmetic operations, Multiply Accumulate ( MAC), direct and inverse trigonometric functions, direct and inverse hyperbolic functions, and exponential functions.