Gianpietro Noto
Improved robustness of FPGA dataflow accelerators for Convolutional Neural Networks.
Rel. Claudio Passerone, Pierpaolo Mori', Giovanni Pollo. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
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Abstract
Neural Networks are computational models that excel at recognizing patterns and extracting meaningful insights from data. Today they have become a pillar of modern technology, powering applications in diverse domains such as image recognition, autonomous driving, and medical diagnostics. As neural networks find their way into safety-critical fields, such as healthcare, aerospace, and automotive systems, the demand for fast, efficient, and reliable inference grows significantly. Moreover, deploying these networks on edge devices, such as IoT sensors, or embedded systems, presents additional challenges due to their limited computational resources and power constraints. To address these challenges, it becomes essential to reduce the size and complexity of neural networks without compromising their performance.
Techniques like model quantization and pruning are vital in achieving this balance
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