MOSFET have dominated the electronic industry for many years. However, the continuous dimensional scaling required to improve the integrated circuit’s performances and reduce the fabrication costs, gives rise to a series of issues. The most relevant one is the so-called Drain-Induced-Barrier- Lowering(DIBL), which consists in a loss of the gate’s control over the channel and results in an increase of the power consumption per chip. To overcome these issues, novel device architectures have been conceived. The most promising one is the Gate-All-Around(GAA) configuration. Moreover, as the gate length reaches the nanometer range, it becomes really challenging to precisely control the dopant atoms distribution and so to construct abrupt pn junctions.