This thesis aims to address the efficiency challenges in data transfer for neuromorphic hardware, which traditionally operate outside the von Neumann architecture paradigm. While neuromorphic hardware excels in mimicking biological neural networks, it still relies on von Neumann systems for data acquisition in many near-future applications. This thesis focuses on designing and implementing a Direct Memory Access (DMA) architecture tailored for neuromorphic applications in System-on-Chip (SoC) to enhance data transfer efficiency. The project specifically investigates optimizing DMA functionality to streamline the data flow between external sources and neuromorphic hardware, ultimately improving overall system performance and energy efficiency. A key aspect of the design involves double buffer ping pong mode, where one buffer is written while the other is read, ensuring continuous data flow.