System-on-Chip (SoC) technologies are crucial in electronics-driven fields, integrating processors, memory, and peripherals into single-chip solutions. These systems offer substantial improvements in performance, energy efficiency, and costs but introduce increasing demands for reliability and security as they grow in complexity. In light of these challenges, Design for Testability (DfT) methodologies are vital, supporting robust testing, diagnosis, and fault isolation. Key DfT features such as Built-In Self-Test (BIST), standardized test access protocols, and fault-tolerant mechanisms enable the development of reliable, high-quality SoCs. This work focuses on the RISC-V Instruction Set Architecture (ISA), which provides an open-source, flexible framework ideal for diverse applications.