Behnam Farnaghinejad
Design and implementation of a RISC-V processor including security features.
Rel. Edgar Ernesto Sanchez Sanchez, Stefano Di Carlo. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
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Abstract
In an age where digital security is paramount, the development of secure and efficient processors is crucial for safeguarding sensitive information and ensuring the integrity of computing systems. As cyber threats evolve in sophistication, there is an increasing demand for hardware-level security features that can provide robust defenses against various attacks. One effective way to make processors more secure is to include special instructions directly in the hardware. This thesis focuses on designing and making a RISC-V processor that has these security features. The goal is to significantly improve the processor's capability to execute cryptography tasks efficiently and securely, leveraging the newly ratified RISC-V Cryptography Extensions.
This research holds substantial significance as it advances secure processor design, which is critical for applications ranging from personal computing to large-scale data centers and vital infrastructure protection
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