Pierfranco Tribuzio
Process Simulation and Compact Modeling for a NS-GAAFET.
Rel. Gianluca Piccinini, Fabrizio Mo, Chiara Elfi Spano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
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Abstract
In the most recent years, semiconductor-based devices and technologies have experienced fast improvements, resulting in important advancements. To enhance their performances, semiconductor devices have been scaled in geometrical dimensions and voltages, following Gordon Moore's laws. However, scaling has led to the emergence of detrimental effects, such as short-channel effects and substrate leakage currents (respectively summarized in the DIBL and SS parameters) forcing designers to seek novel devices and technologies with improved electrostatic control and reasonable drive current and speed. In recent times, an important transition occurred with the introduction of 3D devices such as FinFETs. However, FinFETs have also become inadequate for the technological nodes of today due to some limitations.
In this framework, stacked NanoSheet (NS) GAAFETs (Gate-All-Around Field-Effect Transistors) have been considered the most promising candidates for the replacement of FinFETs for sub-7-nm technological nodes
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