This thesis presents an innovative exploration of the design process of various digital filter IPs used inside a Delta-Sigma ADC. This work has been carried out in collaboration with \textit{Infineon Technologies, Austria} and it is based on the use of High-Level Synthesis (HLS) to create parameterized and reusable digital filters hardware architectures. In this thesis, we focus on Finite Impulse Response (FIR) filters, Polyphase decimation filters and Cascade Integrator Comb (CIC) decimation filters, which are amongst the most common filter structures used in this type of application. The hardware design of these filters is achieved through Siemens EDA HLS tool ‘Catapult’.