The thesis involved conducting a thorough study of some mixed-signal Application-Specific Integrated Circuits (ASIC), creating environments and workflows for their analysis and simulation, and then developing models for analog components of those ASICs. The initial stage of the thesis focused on the training required for dealing with the mixed-signal ASIC. That includes training regarding tools and techniques required for mixed-signal simulation environment setup and operation. The training also included a series of courses on advanced digital verification techniques which covered topics regarding essential SystemVerilog for design and verification, UVM, and SystemVerilog Assertions. Moreover, it included exploring best practices for modeling analog components used inside the mixed-signal ASIC in addition to understanding different modeling techniques and determining which technique to use in the simulation according to the requirements and constraints of the mixed-signal verification.