Duc Tan Tran
Nanoscale simulation of the Atomic Layer Deposition process of Hafnium Dioxide.
Rel. Gianluca Piccinini, Fabrizio Mo, Chiara Elfi Spano, Yuri Ardesi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023
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Abstract
Miniaturisation has been the driving force of the microelectronics industry for the past few decades to achieve more powerful devices. Scaling rules indicate that as the transistor’s channel length is shortened, the gate oxide thickness must also shrink to maintain the electrostatic control of the gate stack while mitigating undesired short-channel effects. However, a thinner insulator layer between the gate and the channel risks amplifying the gate tunnelling current, and thus, increases the power consumption of the device. Therefore, scaled-device manufacturers have switched to utilising high permittivity materials, for example, hafnium dioxide or zirconium dioxide, in substitution of silicon dioxide as the gate dielectrics to prevent excessive gate currents.
Furthermore, the downsizing of the gate oxide brings new challenges to film deposition technologies
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