The problem of incrementing the computational power and memory capacity of digital systems is tightly related to that of scaling the transistor size to improve the transistor density per unit area. As a result, MOS-based technologies have been subjected to extremely strong scaling, with their gate size going from 10 μm to the modern attempts at 3nm technological nodes. This scaling phenomenon has led to approaching sizes at which quantum effects often dominate the behavior of the devices. Rigorous modelling of electronic devices at nanoscale should be based on genuine quantum kinetic approaches, such as the non-equilibrium Green's functions approach self-consistently coupled with Poisson's equation.