This thesis project aims to extend the functionalities of OpenRAM, an open source memory compiler based on Python programming language, capable of generating Static Random Access Memory (SRAM) arrays with adjustable sizes and number of ports by using several technologies, and to characterize the array in terms of power, performance and area about the produced array. The thesis goal consists in enabling OpenRAM to generate and characterize a Register File with 2 read ports and 1 write port by employing a fully open-source design flow and by using SkyWater130 Process Design Kit. The modules needed to build the Register File have been developed in the form of circuit-level and graphic-level descriptions.