Accelerating Deep Neural Networks (DNN) with custom hardware represents an attractive solution to meet stringent applications constraints, especially in mobile/IoT inference scenarios where energy and area efficiency are crucial. Custom hardware is commonly implemented using an iterative process during which the designers identify the main computational and memory patterns of DNN workloads, implement specific hardware structures, and assess the end-to-end performance. As new classes of DNNs are constantly developed and novel reconfigurable platforms, like FPGAs and CGRAs, allow the silicon to be customized after fabrication, agile automation tools are needed to quickly navigate the design space. To this end, in this work, a Python-based framework is proposed to generate tensor systolic arrays, a class of accelerators widely used to perform matrix multiplication, a key operation in DNN workloads.