In the last few years, deep learning algorithms based on neural networks have achieved compelling results in several cognitive tasks, such as computer vision, speech recognition, and natural language processing. Unfortunately, the high accuracy of Deep Neural Networks comes at the cost of enormous memory and computational burden both during the training phase, where the network learns how to perform a task, and during the inference phase, where the model is used on the field. To overcome these challenges and to meet latency and power constraints of various use cases, several domain-specific hardware accelerators have been lately proposed in the literature.