The work of this thesis is focused on the extraction and distribution of internalparameters belonging to the HEENS architecture, which is a scalable Spiking Neural Network emulator. All of the projects are developed by means of the VHDL description, then simulated through the Questa Sim Advanced Simulator and finally synthesized and implemented on a Programmable System on Chip (PSOC), in order to verify time constraints and resources exploitation. In more details, the additions and improvements made to the architecture concern the array of Processing Elements and especially those modules relative to the Address Event Representation over Synchronous Serial Ring Topology, all previously developed by the Integrated Smart Sensors and Health Technologies (ISSET) research group from the Universitat Politècnica de Catalunya (UPC).